Microelectronics: An Integrated Approach.rar ~UPD~
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A fully dense, interconnect stack with metallization for data transfer and power distribution is critical to the performance of high-density, small-scale CMOS integrated circuits (ICs). However, the complexity of the process and the diffusion of the interconnect metallization and semiconductor materials are the main problems that have restricted the implementation of the IC manufacturing process for SiC. Reliability and durability of the interconnect metallization are also critical issues for the future of ICs.
We propose a novel, hybrid device structure using a strain-optimized silicon-on-insulator (SOI) wafer with a thin Si in the buried oxide (BOX) layer (5 nm) for the monolithic integration of high-speed resonant sensors and CMOS circuitry using a standard CMOS foundry process. Our design leverages the attractive combination of the high performance of Si and the low-cost and high reliability of SiO2. We first demonstrate the fabrication and characterization of a generic CMOS-MEMS-based resonant sensor. We then demonstrate the fabrication and characterization of a monolithic CMOS-MEMS-based sensor for acceleration sensing. The high performance of the CMOS-MEMS-based resonant sensor is achieved using the generic design methodology, which is followed by a rigorous optimization of the device geometry and the CMOS layer stack. Finally, we demonstrate the monolithic integration of high-speed resonant sensors and CMOS circuitry using a standard CMOS foundry process.
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